1. Field of the Invention
The present invention relates generally to memory devices and, more particularly, to memory devices adapted to receive input data and provide output data synchronized with a common external clock signal.
2. State of the Art
Integrated circuits, including memory and processors, which operate in synchronization with an external clock signal, typically generate an internal clock signal for gating the rippling nature of logic and for staging synchronous steps. Because of the inherent latencies associated with successive levels of propagation, the internal clock signal may be delayed when compared with the external clock signal. Such a delay may cause deterioration in the performance of the device during high-frequency operation. For example, during operation at high frequencies, the access time (i.e., the time required for outputting data after receipt of an external clock signal) may become longer than the time required for generating an internal clock signal from the received external clock signal.
Approaches have been explored for reducing the deterioration of the performance of a memory device at higher frequencies, one of which approach includes synchronizing the internal clock signal with the external clock signal. One synchronization implementation includes a delay locked loop (DLL), which is used as an internal clock signal generator. DLLs use an adjustable delay line comprised of a series of connectable delay elements. Digital information is used to either include or exclude a certain number of delay elements within a delay line. In a conventional DLL, a clock input buffer accepts a clock input signal and transmits the signal to one or more delay lines of delay elements. The delay of the delay path is increased from a minimum setting until the edge of the delayed reference clock is eventually time-shifted just past the next corresponding edge of the reference clock. As an element of a conventional DLL, a digital phase detector controls the delay line propagation delay so that the delayed clock remains synchronized with the external or reference clock.
Conventional DLLs suffer from numerous drawbacks. External clock signals are susceptible to noise interference, which causes the external clock signal to oscillate around the desired frequency. This oscillation causes the DLL to track the oscillating signal, which results in an extended period of time to establish adequate stability for the DLL to assert a “locked” signal directing internal circuits to rely on the internal clock for synchronization with external circuits. Oscillation may be caused by external clock jitter, phase detection circuit noise interference, and process-voltage-temperature (PVT) variations. Oscillation in the DLL circuit causes extra shift(s) to the DLL delay lines consuming extra unnecessary power resulting in a longer duration in establishing a “locked” state.
A need, therefore, exists to improve the performance of DLLs and overcome, or at least reduce, one or more of the problems set forth above.